The invention relates generally to integrated circuits and, in particular, to structures for a field-effect transistor and methods of forming a structure for a field-effect transistor.
Complementary-metal-oxide-semiconductor processes may be used to build a combination of n-type and p-type field-effect transistors that are used to construct logic gates and that are used as active components in other types of circuits, such as switches found in radiofrequency circuits. Field-effect transistors generally include a channel region, a source, a drain, and a gate electrode. When a control voltage exceeding a characteristic threshold voltage is applied to the gate electrode, carrier flow occurs in the channel region between the source and drain to produce a device output current.
A semiconductor-on-insulator substrate permits device operation at significantly higher speeds with improved electrical isolation and reduced electrical losses in comparison with field-effect transistors built using a bulk silicon wafer. Contingent on the thickness of a device layer of the semiconductor-on-insulator substrate, a field-effect transistor may operate in a fully-depleted mode in which a depletion layer in the channel region extends fully to a buried insulating layer of the semiconductor-on-insulator substrate when typical control voltages are applied to the gate electrode.
The channel region of a p-type field-effect transistor may be composed of silicon-germanium. A conventional approach to form the silicon-germanium channel region is to form a silicon-germanium layer on a portion of the device layer of the semiconductor-on-insulator substrate and to perform a thermal condensation process that transfers the germanium to the device layer. However, silicon-germanium channel regions formed by the thermal condensation of a silicon-germanium layer are limited to having a single germanium content.
Improved structures for a field-effect transistor and methods of forming a structure for a field-effect transistor are needed.